An efficient gate delay model for VLSI design

Accurate estimation of gate delays is essential for timing-related CAD tools. CAD researchers tend to use Elmore delay model for estimating gate delays. Since Elmore delay model was primarily developed for estimating interconnection delay, when applied to gate delay estimation, there will be significant inaccuracy. In this paper, by embedding concepts of electronic theories into switch-level analysis, a simple and efficient delay model for gates of general types (such as NAND, NOR, and complex gates) is proposed. Experimental data show that the proposed gate delay model consistently achieves high accuracy (typically within around 2% of SPICE simulations).