• DocumentCode
    2615414
  • Title

    Highly selective citric buffer etch-stop process for the manufacture of very uniform GaAs/AlGaAs FETs

  • Author

    Schmukler, B.C. ; Brunemeier, P.E. ; Hitchens, W.R. ; Cantos, B.D. ; Strifler, W.A. ; Rosenblatt, D.H. ; Remba, R.D.

  • Author_Institution
    Watkins-Johnson Co., Palo Alto, CA, USA
  • fYear
    1993
  • fDate
    10-13 Oct. 1993
  • Firstpage
    325
  • Lastpage
    328
  • Abstract
    A citric buffer etch has been developed and used to create an optimized etch-stop process for the manufacture of recessed gate GaAs/AlGaAs FETs. Selectives in excess of 1800 have been achieved for a 25 /spl Aring/, x=0.35 Al/sub x/Ga/sub 1-x/As stop layer with the advantage of no iron damage to the channel. Stop layer thicknesses from 15 /spl Aring/ to 100 /spl Aring/ and Al content from x=0.25 to x=0/5 were investigated for process robustness and FET performance. The high selectivity permits the use of a thin 25 /spl Aring/ stop layer of x=0.35 material that does not perturb FET performance, and still provides a robust process. Performance is verified with DC and RF tests, including small signal extrinsic transconductance, and FET noise figure, which are particularly sensitive to increased source resistance. With the etch-stop process, uniformity is greatly enhanced. The standard deviation for Idss was reduced from 20%-30% to less than 5%, and standard deviation for threshold voltage was reduced from 300 mV to less than 30 mV. This proces is applicable to a wide variety of heterostructure devices.<>
  • Keywords
    III-V semiconductors; aluminium compounds; circuit optimisation; etching; gallium arsenide; insulated gate field effect transistors; integrated circuit yield; semiconductor technology; 15 to 100 /spl Aring/; DC tests; FET performance; GaAs; GaAs-AlGaAs; III-V semiconductors; RF tests; citric buffer etch-stop process; high selectivity; noise figure; optimized etch-stop process; process robustness; recessed gate; signal extrinsic transconductance; threshold voltage uniformity; very uniform FET; Etching; FETs; Gallium arsenide; Iron; Manufacturing processes; Noise robustness; RF signals; Radio frequency; Testing; Transconductance;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Gallium Arsenide Integrated Circuit (GaAs IC) Symposium, 1993. Technical Digest 1993., 15th Annual
  • Conference_Location
    San Jose, CA, USA
  • Print_ISBN
    0-7803-1393-3
  • Type

    conf

  • DOI
    10.1109/GAAS.1993.394442
  • Filename
    394442