Current Density and Temperature Distributions in Multilevel Interconnection with Studs and Vwas

Studs and vias are two basic structures in multilevel interconnection. For higher device density and better speed performance inl VLSI technology, the stud or via aspect ratio has to be increased from the present value of 0.5 to about 2.0. The high aspect ratio would raise a reliability concern of current crowding and local heating. In this study, finite element method has been used to calculate the distributions of current density and temperature in multilevel interconnection with studs and vias. The results show that current density peaks in the stud increase with decreasing stud width and thus with increasing aspect ratio. The rate of increase is faster for submicron lines than for wider lines. Current crowding in the via is found to increase with increasing step angle due to the thining down of the step cross-section. The results also indicate that current crowding in the 60° via step region gives rise to a hot spot due to Joule heating. Results of these calculations provide a general approach to optimize the aspect ratio and geometries of stud and via structures for minimal current crowding and local heating in multilevel interconnection.