DocumentCode
2615526
Title
Testing of zipper CMOS logic circuits
Author
Tong, Qiao ; Jha, Niraj K.
Author_Institution
Dept. of Electr. Eng., Princeton Univ., NJ, USA
fYear
1990
fDate
1-3 May 1990
Firstpage
9
Abstract
A method for testing zipper CMOS circuits is presented. A gate-level model for the circuit is derived, and a single stuck-at fault test set for the model is obtained. Vectors are rearranged in the test set so that it can be used to detect single stuck-open and stuck-on faults in addition to stuck-at faults in the zipper CMOS circuit. Faults in the drive circuit are considered
Keywords
CMOS integrated circuits; fault location; integrated logic circuits; logic testing; drive circuit; gate-level model; stuck-at fault test set; stuck-on faults; zipper CMOS logic circuits; CMOS logic circuits; CMOS technology; Circuit faults; Circuit testing; Driver circuits; Electrical fault detection; Logic testing; MOS devices; Monitoring; Semiconductor device modeling;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1990., IEEE International Symposium on
Conference_Location
New Orleans, LA
Type
conf
DOI
10.1109/ISCAS.1990.111900
Filename
111900
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