An error corrector/detector implemented in a desktop programmable gate array

Author

Napolitano, Leonard M., Jr. ; Andaleon, David D. ; Shreeve, William O. ; Redinbo, G.Robert

Author_Institution

Sandia Nat. Lab., Livermore, CA, USA

fYear

1990

fDate

1-3 May 1990

Firstpage

21

Abstract

A complete design is presented for an error detection or correction (EDOC) device based on 32-b data lines to be incorporated as a bidirectional buffer between a processor and the rest of the system. The device is internally fault-tolerant itself. The design includes scan-path capability so that the internal state of the chip can be determined during system testing and debugging. This design can correct single-nibble (4-b) errors or detect double-nibble (8-b) errors, but not both simultaneously. It is implemented in the desktop programmable gate array technology

Keywords

buffer circuits; error correction; error detection; logic arrays; 32 bit; bidirectional buffer; data lines; debugging; desktop programmable gate array; double-nibble errors; error corrector/detector; internal state; internally fault-tolerant; scan-path capability; single-nibble errors; system testing; Circuit faults; Circuit simulation; Detectors; Electrical fault detection; Error correction; Fault tolerance; Integrated circuit interconnections; Programmable logic arrays; Protection; Sensor arrays;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1990., IEEE International Symposium on

Conference_Location

New Orleans, LA

Type

conf

DOI

10.1109/ISCAS.1990.111903

Filename

111903