CMOS logic design with independent-gate FinFETs

Author

Muttreja, Anish ; Agarwal, Niket ; Jha, Niraj K.

Author_Institution

Dept. of Electr. Eng., Princeton Univ., Princeton, NJ

fYear

2007

fDate

7-10 Oct. 2007

Firstpage

560

Lastpage

567

Abstract

Fin-type field-effect transistors (FinFETs) are promising substitutes for bulk CMOS in nano-scale circuits. In this paper, it is observed that in spite of improved device characteristics, high active leakage may remain a problem for FinFET logic circuits. Leakage is found to contribute 31.3% of total power consumption in power-optimized FinFET logic circuits. Various FinFET logic design styles, based on independent control of FinFET gates, are studied. A new low-leakage logic style is presented. Leakage (total) power savings of 64.7% (14.5%) under tight delay constraints and 91.2% (37.2%) under relaxed delay constraints, through the judicious use of FinFET logic styles, are demonstrated.

Keywords

CMOS logic circuits; MOSFET; logic design; logic gates; nanoelectronics; CMOS logic design; Fin-type field-effect transistors; FinFET gates; FinFET logic circuits; bulk CMOS; independent-gate FinFETs; low-leakage logic style; nanoscale circuits; CMOS logic circuits; CMOS technology; Circuit synthesis; Delay estimation; Energy consumption; FinFETs; Logic circuits; Logic design; Logic devices; Switches;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Design, 2007. ICCD 2007. 25th International Conference on

Conference_Location

Lake Tahoe, CA

ISSN

1063-6404

Print_ISBN

978-1-4244-1257-0

Electronic_ISBN

1063-6404

Type

conf

DOI

10.1109/ICCD.2007.4601953

Filename

4601953