Impact of Hot Carriers on Dram Circuits

Hot carrier stress degradation in MOSFETs is well known but its impact on DRAM circuit functionality has not been thoroughly investigated. In this paper observed DRAM degradation with stress is related to the actual transistor level degradation. It is shown here that the transistor saturation drain current is a good monitor of the DRAM Access Time, while the Precharge Time and the Refresh Time can be related respectively to degradations in the transistor´s linear drive current and the saturation region subthreshold current. As concluded in this paper, transistor parameters other than just Vt and gm need to be monitored with hot carrier stress to understand the full impact on DRAM circuit functionality.