DocumentCode
2615736
Title
VLSI architectures for hierarchical block matching algorithms
Author
Komarek, T. ; Pirsch, P.
Author_Institution
Theor. Nachrichtentech. und Inf., Hannover Univ., West Germany
fYear
1990
fDate
1-3 May 1990
Firstpage
45
Abstract
An application-specific multiprocessor system is investigated for real-time implementation of the hierarchical block matching algorithm. The proposed architecture is based on parallel processing units and local memories which are globally preloaded via a common bus. The performance is estimated for the data transfer and the parallel computation time schedule
Keywords
VLSI; computerised picture processing; multiprocessing systems; parallel architectures; real-time systems; VLSI architectures; application-specific multiprocessor system; common bus; data transfer; globally preloaded; hierarchical block matching algorithms; local memories; parallel computation time schedule; parallel processing units; real-time implementation; Computer architecture; Concurrent computing; Matched filters; Motion estimation; Multiprocessing systems; Parallel processing; Processor scheduling; Source coding; Very large scale integration; Video codecs;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1990., IEEE International Symposium on
Conference_Location
New Orleans, LA
Type
conf
DOI
10.1109/ISCAS.1990.111909
Filename
111909
Link To Document