DocumentCode
2615874
Title
VLSI architecture for template matching
Author
Chakrabarti, Chaitali ; JáJá, Joseph
Author_Institution
Maryland Univ., College Park, MD, USA
fYear
1990
fDate
1-3 May 1990
Firstpage
69
Abstract
A systolic architecture for computing real-time template matching is presented. The architecture consists of a multiplier-accumulator and shift registers. The architecture achieves optimal speedup with simple data and control flow. The I/O bandwidth problem is handled by storing part of the input image in the shift registers and by circulating the shift registers so that the processor array can compute on the same input many times
Keywords
VLSI; computerised picture processing; shift registers; systolic arrays; I/O bandwidth problem; VLSI architecture; input image; multiplier-accumulator; optimal speedup; shift registers; systolic architecture; template matching; Bandwidth; Computer architecture; Educational institutions; Filtering; Image edge detection; Layout; Matched filters; Optimal control; Shift registers; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1990., IEEE International Symposium on
Conference_Location
New Orleans, LA
Type
conf
DOI
10.1109/ISCAS.1990.111915
Filename
111915
Link To Document