0.6 V suppy voltage 0.25 /spl mu/m E/D-HJFET(IS/sup 3/T) LSI technology for low power consumption and high speed LSIs

Author

Hida, H. ; Tokushima, M. ; Maeda, T. ; Ishikawa, M. ; Fukaishi, M. ; Numata, K. ; Ohno, Y.

Author_Institution

NEC Corp., Tsukuba, Ibaraki, Japan

fYear

1993

fDate

10-13 Oct. 1993

Firstpage

197

Lastpage

200

Abstract

A new technology for fabricating 0.25 /spl mu/m gate E/D-heterojunction FET LSIs is developed as a step towards the development of ultralow supply voltage LSIs. This technology, which is based upon all dry-process techniques, includes the formation of a 0.25 /spl mu/m gate opening through the use of optical lithography and inner SiO/sub 2/ sidewalls. The f/sub max/ and the g/sub max/ for a Y-shaped gate E-HJFET are 108 GHz and 530 mS/mm, respectively. Excellent performances are obtained with DCFL ring oscillators using n-AlGaAs/i-InGaAs pseudomorphic E/D-HJFETs. These include 18 ps/G unloaded delay and 109 ps/G loaded delay (FI=FO=3, L=1 mm) with 0.15 mW/G at a low supply voltage of 0.6 V, where inverters have a sufficient noise margin of more than 180 mV. Also, 10 Gbps error-free operation of a selector switch is demonstrated with 9.4 mW at 0.6 V.<>

Keywords

III-V semiconductors; JFET integrated circuits; aluminium compounds; direct coupled FET logic; field effect logic circuits; flip-flops; gallium arsenide; indium compounds; integrated circuit interconnections; photolithography; sputter etching; very high speed integrated circuits; 0.25 micron; 0.6 V; 180 mV; 9.4 mW; AlGaAs-InGaAs; DCFL ring oscillators; E/D-HJFET; III-V semiconductor; Y-shaped gate E-HJFET; all dry-process; error-free operation; high speed LSIs; inner SiO/sub 2/ sidewalls; inverters; low power consumption; optical lithography; pseudomorphic; selector switch; ultralow supply voltage; Circuits; Delay; Electron mobility; Energy consumption; FETs; Inverters; Large scale integration; Low voltage; Ring oscillators; Switches;

fLanguage

English

Publisher

ieee

Conference_Titel

Gallium Arsenide Integrated Circuit (GaAs IC) Symposium, 1993. Technical Digest 1993., 15th Annual

Conference_Location

San Jose, CA, USA

Print_ISBN

0-7803-1393-3

Type

conf

DOI

10.1109/GAAS.1993.394470

Filename

394470