Title :
0.1-/spl mu/m GaAs MESFET´s fabricated using ion-implantation and photolithography
Author :
Yamane, Y. ; Nishimura, K. ; Inoue, K. ; Tokumitsu, M.
Author_Institution :
NTT LSI Lab., Kanagawa, Japan
Abstract :
A 0.1 /spl mu/m gate length self-aligned GaAs channel MESFET with a maximum current gain cutoff frequency (f/sub T/) of 113 GHz has been developed. This FET has a planar structure with a selective ion implanted channel layer and self-aligned n/sup +/-layers. The 0.1 /spl mu/m gate length is attained though conventional photolithography and ECR-etching. The tri-level resist technique and two step etching process are developed to attain 0.1 /spl mu/m gate. The demonstration that planar GaAs MESFETs can achieve an f/sub T/ greater than 110 GHz is significant from the view point of LSI fabrication.<>
Keywords :
III-V semiconductors; Schottky gate field effect transistors; gallium arsenide; ion implantation; millimetre wave field effect transistors; photolithography; sputter etching; 0.1 micron; 113 GHz; Au-WSiN gate; ECR-etching; GaAs; III-v semiconductor; LSI fabrication; maximum current gain cutoff frequency; photolithography; planar structure; selective ion implanted channel layer; self-aligned; self-aligned n/sup +/-layers; tri-level resist technique; two step etching process; Etching; FETs; Fabrication; Gallium arsenide; Ion implantation; Large scale integration; Lithography; MESFETs; Resists; Shape;
Conference_Titel :
Gallium Arsenide Integrated Circuit (GaAs IC) Symposium, 1993. Technical Digest 1993., 15th Annual
Conference_Location :
San Jose, CA, USA
Print_ISBN :
0-7803-1393-3
DOI :
10.1109/GAAS.1993.394473
