Title :
High breakdown voltage MESFET with planar gate structure for low distortion power applications
Author :
Kuwata, N. ; Otobe, K. ; Shiga, N. ; Nakajima, S. ; Sekiguchi, T. ; Hashinaga, T. ; Sakamoto, R. ; Matsuzaki, K. ; Nishizawa, H.
Author_Institution :
Sumitomo Electric Ind., Ltd., Yokohama, Japan
Abstract :
A high gate-drain breakdown voltage (V/sub BD/) MESFET with low distortion characteristics was successfully demonstrated. A 0.7 /spl mu/m MESFET with a planar gate structure achieved as high as V/sub BD/ of -19 V with a standard deviation of 2.6 V in a three-inch-diameter GaAs wafer. Power performances evaluated at a 9 V drain bias and 1/2 Idss0 for a 4.8-mm gate periphery device demonstrated a 1 dB compression power (P/sub 1dB/) of 34 dBm with a 47.9% power-added efficiency at 1.5 GHz in A-class operation. A third-order intercept point (IP/sub 3/) of 42 dBm was evaluated at a 4.5 V drain bias and 0.4 Idss0 on a 500 /spl mu/m device at 1.5 GHz. A linearity figure-of-merit of 40.8 was recorded.<>
Keywords :
III-V semiconductors; MESFET integrated circuits; UHF field effect transistors; UHF integrated circuits; field effect MMIC; gallium arsenide; power MESFET; power field effect transistors; power integrated circuits; -19 V; 0.7 micron; 1.5 GHz; 2D device simulation; 47.9 percent; GaAs wafer; III-V semiconductor; LDD; MESFET; high gate-drain breakdown voltage; linearity figure-of-merit; low distortion characteristics; planar gate structure; power MMIC applications; power-added efficiency; third-order intercept point; Doping; Electrodes; Etching; FETs; Gallium arsenide; Laboratories; Linearity; MESFETs; Performance evaluation; Research and development;
Conference_Titel :
Gallium Arsenide Integrated Circuit (GaAs IC) Symposium, 1993. Technical Digest 1993., 15th Annual
Conference_Location :
San Jose, CA, USA
Print_ISBN :
0-7803-1393-3
DOI :
10.1109/GAAS.1993.394474
