Time optimization of AES-256 hardware implementation

In this paper we analyze the hardware implementation of AES crypto algorithm and optimization of the resulting designs in terms of speed. For this purpose, we describes three different implementations of AES-256 algorithm: non-optimized version, version with pipeline and the third version, which was implemented using the structural design style. For each of these versions is given the maximum clock rate at which that design can work. These data were obtained from the development environment Xilinx ISE Design Suite 14.1.