Title :
F-RISC/I: A 32 bit RISC processor implemented in GaAs HMESFET SBFL
Author :
Tien, C.K. ; Lewis, K. ; Philhower, R. ; Greub, H.J. ; McDonald, J.F.
Author_Institution :
Center for Integrated Electron., Rensselaer Polytech. Inst., Troy, NY, USA
Abstract :
F-RISC/I, a reduced version of a fast RISC microprocessor, has been designed and fabricated using IBM´s SBFL standard cell library and Rockwell International´s 0.7 /spl mu/m HMESFET technology. F-RISC/I was designed in six months by two designers using commercial design automation tools. Simulations have shown 400 MHz operation. The chip contains 92,340 transistors on a 7/spl times/7 mm/sup 2/ die and dissipates 3.8 W. The F-RISC/I processor exemplifies the CPU architecture, circuit design, and testing developed to fully take advantage of GaAs technology for high speed computing.<>
Keywords :
III-V semiconductors; MESFET integrated circuits; application specific integrated circuits; carry logic; circuit layout CAD; computer architecture; computer testing; design for testability; field effect logic circuits; gallium arsenide; integrated circuit design; integrated circuit testing; logic CAD; logic testing; reduced instruction set computing; 3.8 W; 32 bit; 400 MHz; CPU architecture; F-RISC/I; HMESFET SBFL; Harvard architecture; III-V semiconductor; SBFL standard cell library; circuit design; datapath architecture; design automation; fast RISC microprocessor; heterostructure MESFET; high speed computing; level-sensitive scan design; reduced version; super-buffered FET logic; testability; Circuit simulation; Circuit synthesis; Circuit testing; Computational modeling; Computer architecture; Design automation; Gallium arsenide; Libraries; Microprocessors; Reduced instruction set computing;
Conference_Titel :
Gallium Arsenide Integrated Circuit (GaAs IC) Symposium, 1993. Technical Digest 1993., 15th Annual
Conference_Location :
San Jose, CA, USA
Print_ISBN :
0-7803-1393-3
DOI :
10.1109/GAAS.1993.394482
