Implementation of a low complexity divider for ILUT-based FPGAs

In this paper we present an efficient approach of high speed divider design using ILUT(Interpolation Look-up Table) method for FPGA implementation. This method can calculate 1/x at a high speed with a low cost circuit configuration. This method can shrink the size of Rom by 98%, when comparing to the simple Look-Up Table method, and much faster than the shifting method because of the inherent advantage of LUT method. The maximum error of this method, comparing to the floating-point result, can be less than 1/2Λ16, when the width of the input data is 16 bits.