A systolic maze-router

Novel hardware for maze routing is proposed. The architecture is based on a systolic hardware that has performed better than the linear array of Rutenbar et al. (1984) and Rutenbar and Atkins (1988). The analysis of a simple case shows that the proposed hardware maintains a high speedup even for very short wires. Although only the routing problem is presently treated, the proposed architecture is very general, and can be easily applied to other DA techniques which require local computation among neighboring cells