A multiple row-based layout generator for CMOS cells

An implementation of a layout generator which follows a multi-row-based layout style is presented. By considering multiple rows in the same cell, it is possible to incorporate the complexity of the inter-row routing in the placement phase. The cell generator is more suitable for circuits that contain both structured and random logic. It is targeted for use in the automatic generation of custom cell libraries. Unlike previous cell generators which consider only the width optimization, the authors´ cell generator tries to minimize the layout area by explicitly considering both dimensions of the layout in the cost function