GaAs Schmitt trigger memory cell design

Author

Law, O.M.K. ; Salama, C.A.T.

Author_Institution

Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada

fYear

1993

fDate

10-13 Oct. 1993

Firstpage

83

Lastpage

86

Abstract

A GaAs five-transistor static memory cell is proposed. It is derived from nMOS Schmitt trigger. The memory cell overcomes the subthreshold leakage loss by using a self ground-shifting technique which limits the leakage current flow to the cell. Compared with conventional GaAs SRAM cells, it offers small design area and allows large memory arrays to be realized. A prototype was implemented in a 1 /spl mu/m non-self aligned GaAs MESFET technology with read and write access time of 1.0 ns and 1.25 ns, respectively.<>

Keywords

III-V semiconductors; MESFET integrated circuits; SRAM chips; field effect memory circuits; gallium arsenide; leakage currents; trigger circuits; 1 micron; 1 ns; 1.25 ns; GaAs; III-V semiconductor; SRAM cells; Schmitt trigger memory cell; five-transistor static memory cell; large memory arrays; nMOS Schmitt trigger; non-self-aligned MESFET; self ground-shifting technique; small design area; subthreshold leakage loss; Gallium arsenide; Leakage current; Logic arrays; MESFETs; MOS devices; MOSFETs; Subthreshold current; Switches; Trigger circuits; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Gallium Arsenide Integrated Circuit (GaAs IC) Symposium, 1993. Technical Digest 1993., 15th Annual

Conference_Location

San Jose, CA, USA

Print_ISBN

0-7803-1393-3

Type

conf

DOI

10.1109/GAAS.1993.394494

Filename

394494