DocumentCode
2616494
Title
On optimizing nMOS and dynamic CMOS functional cells
Author
Chakravarty, S. ; He, Xin ; Ravi, S.S.
Author_Institution
Dept. of Comput. Sci., State Univ. of New York, Buffalo, NY, USA
fYear
1990
fDate
1-3 May 1990
Firstpage
1701
Abstract
The problem of optimizing the layout of nMOS and dynamic CMOS functional cells is addressed. A simple linear-time optimal algorithm is presented for minimizing the width of such cells. A solution to width minimization results in an ordering of the FETs in L . A simple linear-time algorithm is presented for height minimization when an optimal ordering is given. There are a number of FET orderings that minimize the width of the cell. It is shown that finding an optimal FET ordering with minimum height is NP-hard even for series-parallel networks
Keywords
CMOS integrated circuits; MOS integrated circuits; circuit layout; combinatorial circuits; graph theory; integrated logic circuits; logic design; optimisation; FET orderings; MOS gates; dynamic CMOS functional cells layout optimisation; height minimization; linear-time optimal algorithm; nMOS cells layout; optimal ordering; series-parallel networks; width minimization; Combinational circuits; Computer science; FETs; Helium; Integrated circuit interconnections; MOS devices; Minimization methods; NP-hard problem; Wires;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1990., IEEE International Symposium on
Conference_Location
New Orleans, LA
Type
conf
DOI
10.1109/ISCAS.1990.111946
Filename
111946
Link To Document