Title :
A 500 ps 32 /spl times/ 8 register file implemented in GaAs/AlGaAs HBTs [F-RISC/G processor]
Author :
Nah, K. ; Philhower, R. ; Greub, H. ; McDonald, J.F.
Author_Institution :
Center for Integrated Electron., Rensselaer Polytech. Inst., Troy, NY, USA
Abstract :
A high speed register file has been designed that is well-suited for achieving the speed potential of a fast but yield-limited technology such as GaAs/AlGaAs HBT. Descriptions of address driver, write, and threshold voltage generator circuits developed are presented. The test strategy utilizes two linear feedback shift registers (LFSRs) to provide address and data patterns to the register file. A match circuit verifies valid memory function and indicates read access time. The test results indicate a read access time of 500 ps.<>
Keywords :
III-V semiconductors; aluminium compounds; bipolar logic circuits; boundary scan testing; built-in self test; computer testing; current-mode logic; gallium arsenide; heterojunction bipolar transistors; integrated circuit testing; shift registers; 32 bit; 500 ps; F-RISC/G processor; GaAs-AlGaAs; HBT; III-V semiconductor; address line driver; boundary scan scheme; current-mode logic; data patterns; datapath chip; high speed register file; linear feedback shift registers; match circuit; memory function; read access time; sub-nanosecond circuits; test strategy; threshold voltage generator circuits; write circuit; yield-limited technology; Circuit testing; Decoding; Driver circuits; Gallium arsenide; Heterojunction bipolar transistors; Integrated circuit yield; Logic circuits; Registers; Switches; Threshold voltage;
Conference_Titel :
Gallium Arsenide Integrated Circuit (GaAs IC) Symposium, 1993. Technical Digest 1993., 15th Annual
Conference_Location :
San Jose, CA, USA
Print_ISBN :
0-7803-1393-3
DOI :
10.1109/GAAS.1993.394497
