Title :
Delay modeling for GaAs DCFL circuits
Author :
Kayssi, A.I. ; Sakallah, K.A.
Author_Institution :
Dept. of Electr. Eng., American Univ. of Beirut, Lebanon
Abstract :
A timing macromodel for GaAs DCFL logic gates is derived. It circulates the delay of a gate as a function of such parameters as transistor sizes, capacitive loading, fanout, and input transition time. For NOR gates, the simultaneous switching of two inputs is also considered. Calculations based on the derived macromodel show excellent agreement with circuit simulation.<>
Keywords :
III-V semiconductors; circuit analysis computing; delays; direct coupled FET logic; field effect logic circuits; gallium arsenide; integrated circuit modelling; logic gates; timing; DCFL circuits; GaAs; III-V semiconductor; NOR gates; capacitive loading; circuit simulation; delay modelling; dimensional analysis; fanout; input proximity effects; input transition time; inverters; logic gates; macro cell delay; simultaneous switching; timing macromodel; transistor sizes; Capacitance; Delay effects; Driver circuits; Gallium arsenide; Integrated circuit interconnections; Inverters; Logic gates; Propagation delay; Threshold voltage; Timing;
Conference_Titel :
Gallium Arsenide Integrated Circuit (GaAs IC) Symposium, 1993. Technical Digest 1993., 15th Annual
Conference_Location :
San Jose, CA, USA
Print_ISBN :
0-7803-1393-3
DOI :
10.1109/GAAS.1993.394498
