A new dual-material double-gate (DMDG) SOI MOSFET for nanoscale CMOS design

Double-gate (DG) SOI MOSFETs employing asymmetrical gate structure (front gate p⁺ poly and back gate n⁺ poly) are foreseen to be a solution to the scaling limits imposed by bulk MOSFETs. However, for channel lengths below 100 nm, the DG SOI MOSFET is not completely immune to the short-channel effects and in the main challenge in device design. In this paper a new dual-material double-gate (DMDG) SOI MOSFET to overcome this nanoscale regime while simultaneously achieving a higher transconductance and reduced drain induced barrier lowering compared to the DG SOI MOSFET is proposed using two-dimensional simulations. This article further demonstrates a considerable reduction in the peak electric field near the drain end, increased drain breakdown voltage and the desirable threshold voltage "roll-up" even for channel lengths far below 100 nm. The DMDG structure exhibits a step function in the surface potential along the channel. The I_D-V_DS characteristics of both the devices are discussed.