Suppression of DIBL of deep sub-micron FD SOI MOSFETs by source/drain engineering

This article introduces two types of novel FD SOI MOSFETs (fully depleted silicon-on-insulator MOSFET) with novel structures. In first type, p⁺ region is formed under the n⁺ source region only and in the second type, p⁺ region are formed under both the n⁺ source region and the n⁺ drain region. Advantages of these novel devices over conventional FD SOI MOSFETs are confirmed using the device simulator CADDETH. They can suppress DIBL (drain induced barrier lowering) and kink effect significantly in deep sub-micron gate MOSFETs unless the drain voltage exceeds the built-in voltage between the n⁺ and p⁺ regions, maintaining SOI layers or BOX (buried oxide) layers as thick as the conventional devices.