Title :
Circuit performance of double-gate SOI CMOS
Author :
Lin, C.-H. ; Su, P. ; Taur, Y. ; Xi, X. ; He, I. ; Niknejad, A.M. ; Chan, M. ; Hu, C.
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
Abstract :
The paper presents the performance of double-gate MOSFETs (DG MOSFET) in the circuit design perspective is examined via simulation using device structures based on the ITRS specification. The propagation delay (tpd) and energy dissipation of DG CMOS inverter chains with different number of fan-out (FO) are investigated. Load capacitors are added to the output node of each inverter to simulate the parasitic wiring capacitance (Cint) between two stages, assuming reasonable input time and output loading capacitance. The performance result showed superiority of SDG device (symmetric double-gate device) over ADG device (asymmetric double-gate device) in speed and energy efficiency. Performance evaluation indicates that SDG SOI CMOS is the promising device for next generation high performance CMOS technology.
Keywords :
CMOS digital integrated circuits; circuit simulation; integrated circuit design; integrated circuit modelling; mixed analogue-digital integrated circuits; silicon-on-insulator; CMOS inverter chains; CMOS technology; Si; asymmetric double-gate device; circuit design; circuit performance evaluation; circuit simulation; complementary metal-oxide-semiconductor; double-gate MOSFET; double-gate SOI CMOS; energy dissipation; load capacitors; metal-oxide-semiconductor FET; parasitic wiring capacitance; propagation delay; silicon-on-insulator; symmetric double-gate device; CMOS technology; Capacitors; Circuit optimization; Circuit simulation; Circuit synthesis; Energy dissipation; Inverters; MOSFETs; Parasitic capacitance; Propagation delay;
Conference_Titel :
Semiconductor Device Research Symposium, 2003 International
Print_ISBN :
0-7803-8139-4
DOI :
10.1109/ISDRS.2003.1272091
