DocumentCode
2617026
Title
A guaranteed stable order reduction algorithm for packaging and interconnect simulation
Author
Silveira, L.M. ; Elfadel, I.M. ; White, J.K.
Author_Institution
Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA
fYear
1993
fDate
20-22 Oct 1993
Firstpage
165
Lastpage
168
Abstract
A state-space algorithm for model-order reduction based on the balancing of a system realization is presented, with the important characteristic that the reduced order model is guaranteed to be stable. Results are presented demonstrating that the balanced-realization approach generates accurate, stable models, whereas the Pade method is unstable
Keywords
circuit analysis computing; integrated circuit interconnections; integrated circuit packaging; reduced order systems; state-space methods; Pade method; balanced-realization approach; integrated circuits; interconnect simulation; model-order reduction; packaging simulation; reduced order model; stable order reduction algorithm; state-space algorithm; system realisation balancing; Circuit simulation; Computational modeling; Computer simulation; Contracts; Electronics packaging; Integrated circuit interconnections; Integrated circuit packaging; Laboratories; RLC circuits; Transfer functions;
fLanguage
English
Publisher
ieee
Conference_Titel
Electrical Performance of Electronic Packaging, 1993
Conference_Location
Monterey, CA
Print_ISBN
0-7803-1427-1
Type
conf
DOI
10.1109/EPEP.1993.394563
Filename
394563
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