DocumentCode
2617394
Title
A New Test Data Compression Scheme for Multi-scan Designs
Author
Lin, Teng ; Feng, Jianhua ; Wang, Yangyuan
Author_Institution
Dept. of Microelectron., Peking Univ., Beijing
fYear
2007
fDate
9-11 March 2007
Firstpage
179
Lastpage
185
Abstract
In this paper, the authors present a new test data compression scheme for multi-scan designs to reduce the test data volume and thus the test cost. The proposed method achieves the target in two steps. First a drive bit matrix with less columns is generated by exploiting the compatibilities between the columns of the initial scan bit matrix, as well as the inverse compatibilities and the logic dependencies between the columns of the mid bit matrices. Then a dictionary bit matrix with limited rows is constructed, having the properties that for each row of the drive bit matrix a compatible row exists or can be generated by an XOR operation on multiple rows in the dictionary bit matrix, and the total numbers of rows in the dictionary bit matrix used to compute all the compatible rows is minimal. The rows in the dictionary matrix are encoded to further reduce the number of ATE channels and the test data volume. The experimental results for the large ISCAS 89 benchmarks show that the proposed method significantly reduces test data volume for multi-scan designs.
Keywords
automatic test equipment; built-in self test; automatic test equipment; built-in self test; dictionary bit matrix; multi-scan designs; scan bit matrix; test data compression; test data volume reduction; Benchmark testing; Built-in self-test; Costs; Decoding; Dictionaries; Hardware; Logic testing; Microelectronics; Tellurium; Test data compression;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI, 2007. ISVLSI '07. IEEE Computer Society Annual Symposium on
Conference_Location
Porto Alegre
Print_ISBN
0-7695-2896-1
Type
conf
DOI
10.1109/ISVLSI.2007.10
Filename
4208913
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