DocumentCode
2617547
Title
High-speed packaging of second level caches
Author
Gal, Laszlo ; Henderson, Brian
Author_Institution
Unisys Corp., San Diego, CA, USA
fYear
1993
fDate
20-22 Oct 1993
Firstpage
12
Lastpage
15
Abstract
With the ever increasing speed of complex set instruction computer (CISC) and reduced instruction set computer (RISC) microprocessors board wiring delays and package delays are becoming the speed limiting entities in the microprocessor/second level cache systems. These delays are investigated, and approaches to achieve the best performance and cost/performance solutions are presented
Keywords
cache storage; integrated circuit packaging; microprocessor chips; printed circuit accessories; reduced instruction set computing; storage management chips; CISC; MCM-D; RISC microprocessor board wiring delays; complex set instruction computer; cost/performance solutions; high speed packaging; package delays; reduced instruction set computer; second level cache system; Acoustic reflection; Clocks; Costs; Crosstalk; Delay effects; Frequency; Microprocessors; Packaging; Reduced instruction set computing; Wiring;
fLanguage
English
Publisher
ieee
Conference_Titel
Electrical Performance of Electronic Packaging, 1993
Conference_Location
Monterey, CA
Print_ISBN
0-7803-1427-1
Type
conf
DOI
10.1109/EPEP.1993.394602
Filename
394602
Link To Document