Performance Evaluation for Three-Dimensional Networks-On-Chip

Three dimensional (3D) integrated circuits (ICs) are capable of achieving better performance, functionality, and packaging density compared to more traditional planar ICs. On the other hand, networks-on-chip (NoCs) are an enabling solution for integrating large numbers of embedded cores in a single die. 3D NoC architectures combine the benefits of these two new domains to offer an unprecedented performance gain. In this paper, the authors develop a consistent and meaningful evaluation methodology to evaluate the performance of a variety of 3D NoC architectures compared to existing 2D counterparts. The authors demonstrate that the 3D NoCs are capable of achieving higher throughput, lower latency, and lower energy dissipation at the cost of small silicon area overhead.