Title :
A CMOS compatible low power ultra dense capacitor less SOI RAM
Author :
Fazan, P. ; Okhonin, S. ; Nagoga, M.
Author_Institution :
Innovative Silicon S.A., Ecole Polytech. Fed. de Lausanne, Switzerland
Abstract :
This paper presents low power writing mechanisms for the ultra dense capacitor less RAM cell on SOI (silicon-on-insulator). By exploiting band to band tunneling and negative voltages, no current flows in the cell during writing and large programming windows is obtained. First results on data disturb is presented. evidence of a charge pumping related related gate disturb is shown.
Keywords :
CMOS memory circuits; DRAM chips; low-power electronics; semiconductor storage; silicon-on-insulator; CMOS; SOI RAM; Si; band-to-band tunneling; charge pumping; gate disturb; low power writing mechanisms; negative voltages; silicon-on-insulator random access memory; ultra dense capacitor less RAM cell; CMOS technology; Chemical technology; MOSFET circuits; Magnetic materials; Power capacitors; Random access memory; Read-write memory; Tunneling; Voltage; Writing;
Conference_Titel :
Semiconductor Device Research Symposium, 2003 International
Print_ISBN :
0-7803-8139-4
DOI :
10.1109/ISDRS.2003.1272147
