Title :
Novel, High-Speed 16-Digit BCD Adders Conforming to IEEE 754r Format
Author :
Veeramachaneni, Sreehari ; Krishna, M. Kirthi ; Avinash, Lingamneni ; Sreekanth Reddy P ; Srinivas, M.B.
Author_Institution :
Centre for VLSI & Embedded Syst. Technol., Int. Inst. of Inf. Technol., Hyderabad
Abstract :
In view of increasing prominence of commercial, financial and Internet-based applications that process data in decimal format, there is a renewed interest in providing hardware support to handle decimal data. In this paper, a new architecture for efficient 1-digit decimal addition of binary coded decimal (BCD) operands, which is the core of high speed multi-operand adders and floating decimal-point arithmetic, is proposed. Based on this 1-digit BCD adder, novel architectures for higher order (n-digit) BCD adders such as ripple carry adder and carry look-ahead adder are derived. The proposed circuits are compared (both qualitatively as well as quantitatively) with the existing circuits in literature and are shown to perform better. Simulation results show that the proposed 1-digit BCD adder achieves an improvement of 40% in delay. The 16-digit BCD look-ahead adder using prefix logic is shown to perform at least 80% faster than the existing ripple carry one.
Keywords :
adders; digital arithmetic; high-speed integrated circuits; logic design; IEEE 754r format; Internet-based applications; binary coded decimal operands; carry look-ahead adder; decimal addition; decimal data; decimal format; floating decimal-point arithmetic; high speed multioperand adders; high-speed BCD adders; higher order BCD adders; prefix logic; ripple carry adder; Adders; Circuit simulation; Delay; Embedded system; Floating-point arithmetic; Hardware; Humans; Information technology; Internet; Very large scale integration;
Conference_Titel :
VLSI, 2007. ISVLSI '07. IEEE Computer Society Annual Symposium on
Conference_Location :
Porto Alegre
Print_ISBN :
0-7695-2896-1
DOI :
10.1109/ISVLSI.2007.71