A Scalable Modeling Technique to Estimate Dynamic Thermal Design Power of Datapath Intensive Designs

In this paper, a power modeling approach for the estimation of dynamic power under thermal design power (TDP) for datapath intensive designs is proposed. Early estimation of TDP is crucial for the design of thermal and cooling solutions of a chip and for evaluating trade offs of different design alternatives. In this approach, the total switched capacitance and the dynamic power of each partition in the design is estimated as a function of bandwidth and effective toggle rate of the input data transactions. The model considers the impact of cross coupling capacitance on the total switching power besides scaling well for a proliferated design of the existing one. Results have been presented using a complex mobile chipset based on 90nm and having more than 15 million gates