Title :
Vector Processing Support for FPGA-Oriented High Performance Applications
Author :
Yang, Hongyan ; Wang, Shuai ; Ziavras, Sotirios G. ; Hu, Jie
Author_Institution :
Dept. of Electr. & Comput. Eng., New Jersey Inst. of Technol., Newark, NJ
Abstract :
In this paper, we propose and implement a vector processing system that includes two identical vector microprocessors embedded in two FPGA chips. Each vector microprocessor supports floating-point calculations and efficient sparse matrix operations. Dense matrix-matrix multiplication and sparse matrix-vector multiplication with benchmark matrices from various application domains were run on the system to evaluate its performance. The resulting calculation times are compared with those of a commercial PC to show the effectiveness of our approach.
Keywords :
field programmable gate arrays; floating point arithmetic; microprocessor chips; sparse matrices; vector processor systems; FPGA chips; benchmark matrices; dense matrix-matrix multiplication; floating-point calculations; sparse matrix-vector multiplication; vector microprocessors; vector processing system; Arithmetic; Clocks; Field programmable gate arrays; Frequency; Microprocessors; Parallel processing; Registers; Sparse matrices; System-on-a-chip; Vector processors;
Conference_Titel :
VLSI, 2007. ISVLSI '07. IEEE Computer Society Annual Symposium on
Conference_Location :
Porto Alegre
Print_ISBN :
0-7695-2896-1
DOI :
10.1109/ISVLSI.2007.100