A Power Estimation Methodology for QDI Asynchronous Circuits based on High-Level Simulation

In this paper, we present a new efficient methodology for power estimation of QDI asynchronous circuits at pre-synthesized level. Power estimation at high-level is performed by simulating the intermediate format of the design. This format consists of concurrent processes. The number of reads and writes accesses on processes ports are counted by analyzing the conditional and computational portion during the simulation. To verify the accuracy of our presented method we applied it to Reed-Solomon as the benchmark. The simulation results show (15-20) % average error in comparison with the power measured by SPICE.