DocumentCode :
2618380
Title :
Reliable Binary Signed Digit Number Adder Design
Author :
Kharbash, F. ; Chaudhry, G.M.
Author_Institution :
Dept. of Comput. Sci. & Electr. Eng., Missouri Univ., Kansas, MO
fYear :
2007
fDate :
9-11 March 2007
Firstpage :
479
Lastpage :
484
Abstract :
The binary signed digit number (BSDN) system is used implicitly or explicitly to speed up arithmetic operations in many digital systems. This is due to its capability of carry-free addition and regular layout. Also, with the proper selection of the encoding scheme used to encode the BSDN digit set D = {-1, 0, 1} into binary bits, an error detection capability feature can be gained. In this work, we present the design of BSDN full adder cell using the 1-out-of-3 encoding with and without error detection capability. Synthesis results showed that the carry-free addition feature of the BSDN adder is preserved in the proposed design regardless of the inputs size. Also the overall adder performance depends on the desired level of error detection and the effectiveness of the used BSDN full adder.
Keywords :
adders; digital arithmetic; logic design; 1-out-of-3 encoding; arithmetic operations; binary bits; binary signed digit number adder; carry-free addition; error detection capability; full adder cell; Adders; Circuits; Cities and towns; Computer science; Computer vision; Digital arithmetic; Digital systems; Electrical fault detection; Encoding; Error correction;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI, 2007. ISVLSI '07. IEEE Computer Society Annual Symposium on
Conference_Location :
Porto Alegre
Print_ISBN :
0-7695-2896-1
Type :
conf
DOI :
10.1109/ISVLSI.2007.88
Filename :
4208966
Link To Document :
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