DocumentCode :
2618474
Title :
Design of A Double-Precision Floating- Point Multiply-Add-Fused Unit with Consideration of Data Dependence
Author :
Li, Zhaolin ; Li, Gongqiong
Author_Institution :
Res. Inst. of Inf. Technol., Tsinghua Univ.
fYear :
2007
fDate :
9-11 March 2007
Firstpage :
492
Lastpage :
497
Abstract :
A floating-point multiply-add-fused unit with data dependence considered is proposed in this paper. It is implemented in three pipeline stages. The main improvement is that the intermediate computation results are fed back to the first stage and floating-point operations can be executed directly following their preceding floating-point operations without being stalled due to data dependence. The experiment results show that 20% performance increase can be attained at the cost of only 0.16ns time delay added to the critical path.
Keywords :
adders; delays; floating point arithmetic; logic design; multiplying circuits; 16 ns; data dependence; floating-point multiply-add-fused unit; floating-point operations; pipeline stages; time delay; Computer architecture; Costs; Data analysis; Delay; Hardware; Microprocessors; Performance analysis; Pipelines; Process design; Research and development;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI, 2007. ISVLSI '07. IEEE Computer Society Annual Symposium on
Conference_Location :
Porto Alegre
Print_ISBN :
0-7695-2896-1
Type :
conf
DOI :
10.1109/ISVLSI.2007.37
Filename :
4208970
Link To Document :
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