Title :
A comparison of low power architectures for digital delay measurement
Author :
Martin-Pirchio, Franco ; Chacón-Rodríguez, Alfonso ; Julián, Pedro ; Mandolesi, Pablo
Author_Institution :
Departamento de Ingenieria Electrica y Computadoras, Univ. Nacional del Sur, Bahia Blanca
Abstract :
Two different versions of a method for the calculation of the delay between two digital signals with central frequencies in the range [20, 300] Hz are compared in terms of their power dissipation. Power dissipation simulations are run on both versions from their layout on a 0.35mum technology. The second version shows a cut of 37% in total dissipation under the same test conditions.
Keywords :
delays; integrated circuit design; integrated circuit measurement; low-power electronics; 0.35 micron; 20 Hz; 300 Hz; digital delay measurement; digital signals; low power architectures; power dissipation simulations; Computer architecture; Counting circuits; Delay effects; Delay estimation; Energy consumption; Measurement standards; Power dissipation; Power measurement; Registers; Synchronization;
Conference_Titel :
VLSI, 2007. ISVLSI '07. IEEE Computer Society Annual Symposium on
Conference_Location :
Porto Alegre
Print_ISBN :
0-7695-2896-1
DOI :
10.1109/ISVLSI.2007.3
