A Low-Power High-Speed 4-Bit ADC for DS-UWB Communications

Author

Agdam, M.K. ; Nabavi, A.

Author_Institution

Dept. of Electr. Eng., Tarbiat Modarres Univ., Tehran

fYear

2007

fDate

9-11 March 2007

Firstpage

506

Lastpage

507

Abstract

This paper describes a 4-bit 4GS/s flash analog to digital converter for DS-UWB applications, using a 0.18 mum CMOS technology. The converter utilizes full custom logic, low noise preamplifiers, and fast comparators with inductive loads. The analog and digital power supplies are 1.8V and 2.2V, respectively, and the power dissipation is only 68-mW. Averaging resistance networks are used which improves the offset voltages by a factor of 2, and reduces both the INL and DNL as illustrated by Monte Carlo simulation. The differential input swing is 1V_pp at 1.8-V supply. Simulated performance for 4GS/s shows 22.2 dB of SNDR at 1.5-GHz input frequency. The INL is -0.31/0.35 LSB, and the DNL is -0.18/0.25 LSB. Using averaging technique decreases these errors to -0.2/+0.18LSB and -0.13/+0.1LSB, respectively

Keywords

CMOS integrated circuits; Monte Carlo methods; UHF integrated circuits; analogue-digital conversion; comparators (circuits); low noise amplifiers; low-power electronics; mixed analogue-digital integrated circuits; ultra wideband communication; 0.18 micron; 1.5 GHz; 1.8 V; 2.2 V; 4 bit; 68 mW; CMOS technology; DS-UWB communications; Monte Carlo simulation; fast comparators; flash analog to digital converter; full custom logic; inductive loads; low noise preamplifiers; low-power high-speed ADC; resistance networks; Analog-digital conversion; CMOS technology; Circuits; Frequency; Latches; Logic gates; Power dissipation; Power supplies; Preamplifiers; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI, 2007. ISVLSI '07. IEEE Computer Society Annual Symposium on

Conference_Location

Porto Alegre

Print_ISBN

0-7695-2896-1

Type

conf

DOI

10.1109/ISVLSI.2007.7

Filename

4208973