Title :
An overview of BiCMOS technology and applications
Author :
Alvarez, A.R. ; Pai, S.Y. ; Ratnakumar, K.N. ; Gibbs, G. ; Ramirez, R. ; Koh, Y.J. ; Robins, S.T. ; Segal, J. ; LaBouff, M.J. ; Kanegawa, K. ; Solfest, R.W. ; Kupec, J.D. ; Lutz, R.C.
Author_Institution :
Cypress/Aspen Semicond., San Jose, CA, USA
Abstract :
BiCMOS technology significantly enhances speed performance while incurring a negligible power or area penalty. BiCMOS can therefore provide applications with CMOS power and densities at speeds which were previously the exclusive domain of bipolar. This has been demonstrated in applications ranging from static RAMs to gate arrays to microprocessors. Thus, the concept of a system on a chip becomes a reality with BiCMOS. The main disadvantage of BiCMOS is greater process complexity, which results in a 1.1-1.3×packaged chip cost. BiCMOS is currently being demonstrated at 0.5 μm. This will extend the conventional |5-V| TTL (transistor-transistor logic) and ECL (emitter-coupled logic) interfaces to the next level of technology. The BiCMOS challenge has shifted from process and technology to circuits and systems
Keywords :
BIMOS integrated circuits; digital integrated circuits; integrated circuit technology; reviews; 0.5 micron; 5 V; BiCMOS technology; ECL; TTL; emitter-coupled logic; gate arrays; microprocessors; packaged chip; static RAM; transistor-transistor logic; BiCMOS integrated circuits; CMOS process; CMOS technology; Circuit noise; Circuits and systems; Computer aided engineering; Costs; Fuses; MOSFET circuits; Power dissipation;
Conference_Titel :
Circuits and Systems, 1990., IEEE International Symposium on
Conference_Location :
New Orleans, LA
DOI :
10.1109/ISCAS.1990.112104
