ISAID-a methodology for automated analog IC design

A methodology called ISAID for the automated generation of analog integrated circuit designs is presented. The methodology makes use of a hierarchical design procedure to break down the required system specifications into transistor descriptions. The methodology provides a correction procedure which enables designs which fail to meet the required specifications when simulated or laid out to be corrected either by altering circuit component sizes or by making changes in the designed topology itself. Some approaches to analog IC design are briefly reviewed. A two-stage operational amplifier design example is presented