A New Binomial Mapping and Optimization Algorithm for Reduced-Complexity Mesh-Based On-Chip Network

Author

Wein-Tsung Shen ; Chih-Hao Chao ; Yu-Kuang Lien ; An-Yeu Wu

Author_Institution

Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei

fYear

2007

fDate

7-9 May 2007

Firstpage

317

Lastpage

322

Abstract

This paper presents an efficient binomial IP mapping and optimization algorithm (BMAP) to reduce the hardware cost of on-chip network (OCN) infrastructure. The complexity of BMAP is O(N²log(N)). Based on our OCN system synthesis flow, the proposed algorithm provides more economic network component mapping in comparison with traditional OCN mapping algorithm. The experimental result shows total traffic on network is reduced by 37% and average network hop count is reduced by 46%. With further optimization, the hardware efficiency is enhanced therefore the total hardware cost of network infrastructure is reduced to 51%~85%

Keywords

circuit complexity; circuit optimisation; network-on-chip; OCN system synthesis flow; binomial IP mapping; economic network component mapping; optimization algorithm; reduced-complexity mesh-based on-chip network; Cost function; Design optimization; Hardware; Network interfaces; Network synthesis; Network topology; Network-on-a-chip; Scalability; Telecommunication traffic; Traffic control;

fLanguage

English

Publisher

ieee

Conference_Titel

Networks-on-Chip, 2007. NOCS 2007. First International Symposium on

Conference_Location

Princeton, NJ

Print_ISBN

0-7695-2773-6

Type

conf

DOI

10.1109/NOCS.2007.5

Filename

4209026