Title :
Resistorless Bi-CMOS logic circuit
Author :
Javan, H. ; Chamas, H.
Author_Institution :
Dept. of Electr. Eng., State Univ. of New York, New Paltz, NY, USA
Abstract :
A logic circuit design which combines bipolar emitter coupled logic (ECL) and CMOS technology with extremely low power consumption and low propagation delay is introduced. The calculated and the simulated results show that the power-speed product is 12.5 P-J which is 35 P-J less than the conventional Motorola ECL-10 k. Simulated results show that the proper operation of the circuit requires an optimum bias of 1.5 V. The corresponding maximum peak transient power is 17 mW, while the maximum RMS power is about 10 mW
Keywords :
BIMOS integrated circuits; emitter-coupled logic; integrated logic circuits; logic design; 1.5 V; 10 mW; 17 mW; BiCMOS IC; CMOS technology; ECL; bipolar emitter coupled logic; logic circuit design; low power consumption; low propagation delay; maximum RMS power; maximum peak transient power; CMOS logic circuits; CMOS technology; Capacitance; Circuit simulation; Coupling circuits; Energy consumption; Fabrication; Logic circuits; MOSFETs; Resistors;
Conference_Titel :
Circuits and Systems, 1990., IEEE International Symposium on
Conference_Location :
New Orleans, LA
DOI :
10.1109/ISCAS.1990.112116
