An accurate analytical delay model for BiCMOS driver circuits

An analytical delay model for BiCMOS driver circuits which is based on physical device parameters and can be used to estimate both the pull-up and the pull-down times for a variety of circuit configurations is presented. The intrinsic delay associated with the bipolar transistors is taken into consideration by a charge control model that incorporates the high-injection effects upon the current gain and the base transport factor. Separate sets of delay equations are derived for the pull-up and pull-down transient responses because significant differences are shown to exist between the two cases. A comparison with SPICE circuit simulation results shows that the model predicts the respective delay times with less than 10% error in most cases. The influence of device dimensions upon the inverter delay time is investigated. It is demonstrated than an optimal area allocation exists between the CMOS and bipolar parts of the driver circuit when the total available area is limited, such as in standard cell configurations