A high-speed CMOS full-adder cell using a new circuit design technique-adaptively-biased pseudo-NMOS logic

Author

Lu, Fang ; Samueli, Henry

Author_Institution

Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA

fYear

1990

fDate

1-3 May 1990

Firstpage

562

Abstract

A circuit design technique called adaptively biased pseudo-NMOS logic (APNL) is investigated and used in a differential-type full-adder cell design. Based on the layout and simulation results, the APNL full-adder cell is nearly 80% faster than conventional cascode voltage switch logic (CVSL) and over 30% faster than the domino CVSL circuits, while consuming comparable power and silicon area. An application example of the APNL technique is described

Keywords

CMOS integrated circuits; adders; integrated logic circuits; logic design; CMOS full-adder cell; adaptively-biased pseudo-NMOS logic; circuit design technique; differential-type; high-speed; layout; Adders; CMOS logic circuits; CMOS process; Circuit synthesis; Delay; Digital signal processing chips; Logic circuits; Logic design; MOSFET circuits; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1990., IEEE International Symposium on

Conference_Location

New Orleans, LA

Type

conf

DOI

10.1109/ISCAS.1990.112118

Filename

112118

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2619415