Title :
A novel design of binary majority gate and its application to median filtering
Author :
Lee, Charng Long ; Jen, Chein-Wei
Author_Institution :
Inst. of Electron., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Abstract :
A majority gate composed of output-wired inverters is proposed. A simple circuit for the majority gate constructed by conventional CMOS inverters is presented. The transistors are fewer and the delay time is constant, regardless of input numbers. A bit-level median filtering algorithm is presented as an application. The incorporation of the majority gate into the median filter is described. A flexible design for the median filter is presented
Keywords :
CMOS integrated circuits; digital filters; integrated logic circuits; logic design; logic gates; CMOS inverters; binary majority gate; bit-level median filtering algorithm; logic circuits; output-wired inverters; Artificial neural networks; Circuits; Computer applications; Computer networks; Decision making; Fault tolerant systems; Filtering algorithms; Filters; Inverters; Voltage;
Conference_Titel :
Circuits and Systems, 1990., IEEE International Symposium on
Conference_Location :
New Orleans, LA
DOI :
10.1109/ISCAS.1990.112123
