A new two-phase pipelined dynamic CMOS ternary logic

A dynamic CMOS ternary logic circuit is developed which can be used to form a pipelined system using two-phase nonoverlapped clocks. The ternary inverters have a full voltage swing without DC power dissipation. For complex ternary logic, a circuit structure called simple ternary differential logic (STDL) is proposed and analyzed. STDL has the same advantages as binary differential logic-low power dissipation, small layout area, short circuit delay, and high logic design flexibility. There also exists a dead band from -0.2 V to 0.2 V in STDL which can suppress transient disturbances and retain the correct circuit state. The design procedure of STDL is developed. It is shown that all the dynamic ternary logic circuits developed have the advantages of high speed, lower power dissipation, and no race problems