200-Mb wafer scale memory

A wafer scale memory has now been developed that has achieved a high enough yield to make it practical to manufacture. This CMOS wafer scale memory was developed with high density and low cost as higher priorities than high speed. The device fills a gap in the hierarchy of computer memory between high speed, high priced main memory and low speed, low priced off-line or hard disk memory. To achieve high density, standard 1-Mb DRAMs with a small amount of control logic were arranged as an array on the wafer. Partially good DRAMs are used as the basis for these devices, and several redundancy techniques requiring no additional process steps are used to increase yield. Since the number of wire bonds and solder joints was reduced by 90% compared to the same device manufactured using discrete DRAM chips, the reliability factor of these devices was greatly increased