Title :
2.3 60Gb/s NRZ and PAM4 transmitters for 400GbE in 65nm CMOS
Author :
Ping-Chuan Chiang ; Hao-Wei Hung ; Hsiang-Yun Chu ; Guan-Sing Chen ; Jri Lee
Author_Institution :
Nat. Taiwan Univ., Taipei, Taiwan
Abstract :
Recent research indicates that data-link transceivers running at or below 40Gb/s are practical to implement in CMOS technology [1]. However, next-generation datacom and telecom systems require transceivers to operate at even higher data rates. For example, a 400Gb/s Ethernet system may need 8×50Gb/s PAM2 (NRZ) or PAM4 channels [2]. This paper introduces fully integrated solutions for NRZ and PAM4 transmitters. The 60Gb/s operating speed demonstrates sufficient bandwidth even for standards with coding overhead.
Keywords :
CMOS integrated circuits; local area networks; transceivers; CMOS technology; Ethernet system; NRZ; PAM4 channels; PAM4 transmitters; bit rate 400 Gbit/s; bit rate 60 Gbit/s; coding overhead; data-link transceivers; next-generation datacom system; next-generation telecom systems; size 65 nm; CMOS integrated circuits; Clocks; Optical signal processing; Phase locked loops; Power transmission lines; Synchronization; Transmitters;
Conference_Titel :
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2014 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4799-0918-6
DOI :
10.1109/ISSCC.2014.6757329
