Results of an on pixel sparsification architecture in a MAPS test chip in STM 130nm technology

The paper presents a new approach for sparsification using only NMOS transistors to implement the on pixel signal processing. The use of PMOS transistors would create competing N-well that would drain part of the signal charge. The architecture that, using about seventy transistors, implements: correlated double sampling, signal discrimination and analog information storing on each pixel is briefly described. The test chip, submitted as a multiproject run in the STMicroelectronics 130nm technology, is described. The first results of the chip characterization with radioactive sources, some preliminary test beam data and the threshold dispersion measurements for the digital part of the sparsified architecture is presented.