Title :
2.4 A 25Gb/s 5.8mW CMOS equalizer
Author :
Jun Won Jung ; Razavi, Behzad
Author_Institution :
Univ. of California, Los Angeles, Los Angeles, CA, USA
Abstract :
The power consumption of broadband receivers becomes particularly critical in multi-lane applications such as the 100 Gigabit Ethernet. However, the powerspeed trade-off tends to intensify at higher rates, making it a greater challenge to reach the generally-accepted efficiency of 1mW/Gb/s. Prominent among the power-hungry receiver building blocks are the clock-and-data-recovery circuit, the deserializer, and the front-end equalizer. The use of charge-steering techniques has shown promise for the low-power implementation of the first two functions [1]. This paper introduces a half-rate 25Gb/s equalizer employing charge steering and achieving an efficiency of 0.232mW/Gb/s.
Keywords :
CMOS integrated circuits; clock and data recovery circuits; equalisers; radio receivers; CMOS equalizer; Ethernet; bit rate 25 Gbit/s; broadband receivers; charge steering; clock-and-data-recovery circuit; deserializer; front-end equalizer; power 5.8 mW; power consumption; receiver building blocks; CMOS integrated circuits; CMOS technology; Clocks; Decision feedback equalizers; Latches; Receivers;
Conference_Titel :
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2014 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4799-0918-6
DOI :
10.1109/ISSCC.2014.6757330
