Title :
2.7 A coefficient-error-robust FFE TX with 230% eye-variation improvement without calibration in 65nm CMOS technology
Author :
Seungho Han ; Sooeun Lee ; Minsoo Choi ; Jae-Yoon Sim ; Hong-June Park ; Byungsub Kim
Author_Institution :
Pohang Univ. of Sci. & Technol., Pohang, South Korea
Abstract :
This paper presents a 4-tap coefficient-error-robust feed-forward equalization (FFE) transmitter (TX) for massively parallel links. Recently, massively parallel links such as on-chip links [1-3], silicon interposers [4,5], or wide I/Os [6] are gaining popularity to meet increasing demand for data transmission with a limited power budget. However, calibration overhead for thousands I/Os to compensate coefficient errors due to nano-scale variation has a high hardware cost. To reduce this overhead, we develop a coefficient-error-robust FFE (B-FFE) TX architecture that uses the channel loss to suppress eye perturbation due to coefficient errors while behaving identically to a conventional FFE.
Keywords :
CMOS integrated circuits; equalisers; error compensation; feedforward; transmitters; 4-tap coefficient-error-robust feedforward equalization transmitter; B-FFE TX architecture; CMOS technology; FFE TX architecture; calibration overhead; coefficient error compensation; coefficient-error-robust FFE TX; data transmission; eye perturbation suppression; eye-variation improvement; limited power budget; massively parallel links; nanoscale variation; on-chip links; silicon interposers; size 65 nm; wide I/Os; CMOS integrated circuits; CMOS technology; Calibration; Current measurement; Mirrors; System-on-chip; Transceivers;
Conference_Titel :
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2014 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4799-0918-6
DOI :
10.1109/ISSCC.2014.6757333